View DS3906_279781.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Rev 0; 4/05
Triple NV Low Step Size Variable Resistor Plus Memory
General Description
The DS3906 is intended for low resistance, small stepsize applications. It contains three nonvolatile (NV), lowtemperature coefficient, variable digital resistors that are capable of ohm and subohm increments when used in parallel with a fixed external resistor. All three of the DS3906's resistors have 64 positions (plus a high-Z state) with a pseudo-log response cleverly chosen to have a linear equivalent resistance when paired with an external resistor (see graphs below). The DS3906 also contains 16 bytes of user EEPROM that, in addition to the resistors, are controlled through an I2CTM-compatible serial interface. Three address pins allow up to eight DS3906s to be placed on the same I2C bus. The DS3906 can also be factory cutomized to provide a variety of transfer functions depending on user requirements. Contact mixedsignal.apps@dalsemi.com for additional information.
Features
Three Programmable Resistors for Low Step-Size Applications (Ohm and Subohm) Resistor Settings are NV 16-Byte NV User Memory (EEPROM) I2C-Compatible Serial Interface Up to 8 Devices Can be Multidropped on the Same I2C Bus Low Power Consumption Wide Operating Voltage (2.7V to 5.5V) Operating Temperature Range: -40C to +85C
DS3906
Ordering Information
PART DS3906U DS3906U+ TEMP RANGE -40C to +85C -40C to +85C PACKAGE 10-Pin SOP 10-Pin SOP
Applications
Low Ohm, Fine Resolution Driver Control for LED Display Panels Low Ohm, Fine Resolution Instrumentation Control
+Denotes lead-free package. Add "/T&R" for Tape-and-Reel orders
Pin Configuration
TOP VEIW A1 1 SDA 2 SCL 3 10 A2 9 A0 H0 H1 H2
Typical Operating Circuit appears at end of data sheet.
VCC GND
4 5
DS3906
8 7 6
10-PIN SOP
Resistor Plots
RESISTOR 0 AND 1 RESISTANCE vs. POSITION (WITH AND WITHOUT EXTERNAL RESISTOR)
200 180 REFFECTIVE = R0, 1 || REXT () 160 140 120 100 80 60 40 20 0 0 16 32 20 R0, 1 WITHOUT REXT 48 64 0 R2 REXT2 50 0 0 16 32 48 64 RESISTOR POSITION (dec) R0, 1 || (REXT = 50) 100 500 R0, 1 || (REXT = 105) R0, 1 || (REXT = 150) R0, 1 WITHOUT REXT () 2000 1500 3000 2500 REFFECTIVE = R2 || REXT () R0 REXT0
RESISTOR 2 RESISTANCE vs. POSITION (WITH AND WITHOUT EXTERNAL RESISTOR)
350 R2 || (REXT = 400) 300 250 200 1000 150 100 R2 WITHOUT REXT 600 400 R2 || (REXT = 250) 800 R2 || (REXT = 310) 1400 1200 R2 WITHOUT REXT () 1600
DS3906 R1
REXT1
RESISTOR POSITION (dec)
I2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips Corp. ______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Triple NV Low Step Size Variable Resistor Plus Memory DS3906
ABSOLUTE MAXIMUM RATINGS
Voltage on VCC, SDA, SCL, and H0-H2 Pins Relative to Ground.............................................-0.5V to +6.0V Voltage on A0, A1, and A2 Relative to Ground .....-0.5V to VCC + 0.5V, not to exceed +6.0V Resistor Current ....................................................................5mA Operating Temperature Range ...........................-40C to +85C EEPROM Programming Temperature Range .........0C to +70C Storage Temperature Range ............................-55C to +125C Soldering Temperature...................See J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Supply Voltage Input Logic 1 Input Logic 0 Resistor Inputs Resistor Current SYMBOL VCC VIH VIL H0, H1, H2 VCC = 2.7V to 5.5V IR (Note 1) CONDITIONS MIN +2.7 0.7 x VCC -0.3 -0.3 TYP MAX +5.5 VCC + 0.3 0.3 x VCC +5.5 5 UNITS V V V V mA
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Standby Current (Note 2) Input Leakage for All Pins Low-Level Output Voltage (SDA) I/O Capacitance SYMBOL ISTBY IL VOL SDA CI/O 3V 5V (Note 3) 3mA sink current 6mA sink current -1.0 0 0 CONDITIONS MIN TYP 130 160 250 +1.0 0.4 0.6 10 MAX UNITS A A V pF
ANALOG RESISTOR CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Resistor Tolerance INL DNL Temperature Coefficient Resistor High-Z Resistors RHIGH-Z Guaranteed monotonic by design SYMBOL (Note 4) (Note 4) At position 3Fh (Note 8) 5.5 CONDITIONS From nominal values in Table 3 MIN -20 -2 -0.5 60 TYP MAX +20 +2 +0.5 UNITS % LSB LSB ppm/C M
2
_____________________________________________________________________
Triple NV Low Step Size Variable Resistor Plus Memory
AC ELECTRICAL CHARACTERISTICS (See Figure 2)
(VCC = +2.7V to 5.5V, TA = -40C to +85C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).)
PARAMETER SCL Clock Frequency Bus Free Time Between Stop and Start Conditions Hold Time (Repeated) Start Condition Low Period of SCL High Period of SCL Data Hold Time Data Set-up Time Start Set-up time SDA and SCL Rise Time SDA and SCL Fall Time Stop Set-up Time SDA and SCL Capacitive Loading EEPROM Write Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tWR (Note 6) (Note 7) (Note 6) (Note 6) (Note 5) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 20 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms
DS3906
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to 5.5V)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EEPROM Writes
0C to +70C. The room temperature specification is at least 4x better than specification over 0C to +70C.
50,000
Note 1: All voltages referenced to ground. Note 2: ISTBY is specified with SDA = SCL = VCC, resistor pins floating, and inputs tied to VCC or GND. Note 3: The DS3906 will not obstruct the SDA and SCL lines if VCC is switched off as long as the voltages applied to these input do not violate their minimum and maximum input voltage levels. Note 4: Tested with external resistor of 87 for R0 and R1 and 258 for R2 at 25C. Note 5: Timing shown is for fast mode (400kHz) operation. This device is also backward compatible with I2C standard mode timing. Note 6: CBtotal capacitance of one bus line in picofarads. Note 7: The EEPROM write time begins after a stop condition occurs. Note 8: Guaranteed by design.
_____________________________________________________________________
3
Triple NV Low Step Size Variable Resistor Plus Memory DS3906
Typical Operating Characteristics
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS3906 toc01
SUPPLY CURRENT vs. TEMPERATURE
DS3906 toc02
SUPPLY CURRENT vs. SCL FREQUENCY
180 160 SUPPLY CURRENT (A)
DS3902 toc03
200 180 160 SUPPLY CURRENT (A) 140 120 100 80 60 40 20 0 2.70 3.20 3.70 4.20 4.70 5.20 SUPPLY VOLTAGE (V)
180 160 SUPPLY CURRENT (A) 140 120 100 80 60 40 20 0 -40 -15 10 35 60 SDA/SCL = VCC ADDRESS PINS CONNECTED TO GND VCC = 3.3V VCC = 5V
200
140 120 100 80 60 40 20 0 VCC = SDA = 5V ADDRESS PINS CONNECTED TO GND 0 50 100 150 200 250 300 350 400 SCL FREQUENCY (kHz)
85
TEMPERATURE (C)
RESISTORS (R0,1) vs. RESISTOR SETTING
DS3906 toc04
RESISTOR R2 vs. RESISTOR SETTING
DS3906 toc05
RESISTANCE (R0,1 REXT) vs. RESISTOR SETTING
80 RESISTANCE (R0,1 REXT) () 70 60 50 40 30 20 10 0 REXT = 87
DS3906 toc06
3000 2500 RESISTORS (R0,1) () 2000 1500 1000 500 0 0 10 50 RESISTOR SETTING (dec) 20 30 40 60
1600 1400 1200 RESISTOR (R2) () 1000 800 600 400 200 0
90
70
0
10
50 RESISTOR SETTING (dec)
20
30
40
60
70
0
10
50 30 20 40 RESISTOR SETTING (dec)
60
70
DS3906 toc07
RESISTANCE (R2 REXT) ()
200 REXT = 258 150
200 150 100 50 0 -50 0 10 50 30 20 40 RESISTOR SETTING (dec) 60 -40C TO +25C
100
50
0 0 10 50 30 20 40 RESISTOR SETTING (dec) 60 70
70
4
_____________________________________________________________________
DS3906 toc08
250
RESISTOR R0,1 TEMPERATURE COEFFICIENT (ppm/C)
RESISTANCE (R2 REXT) vs. RESISTOR SETTING
RESISTOR R0,1 TEMPERATURE COEFFICIENT (-40C TO +25C) vs. RESISTOR SETTING
250
Triple NV Low Step Size Variable Resistor Plus Memory DS3906
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
RESISTOR R0,1 TEMPERATURE COEFFICIENT (ppm/C)
DS3906 toc09
DS3906 toc10
350 +25C TO +85C 300 250 200 150 100 50 0 0 10 50 30 20 40 RESISTOR SETTING (dec) 60
10 -40C TO +25C 5 0 -5 -10 -15 -20 -25 0 10 50 30 20 40 RESISTOR SETTING (dec) 60
160 140 120 100 80 60 40 20 0 0 10
+25C TO +85C
70
70
50 30 20 40 RESISTOR SETTING (dec)
60
70
RESISTANCE vs. SUPPLY VOLTAGE
DS3906 toc12
R0,1 RESISTANCE AT POSITION 2Fh vs. POWER-UP VOLTAGE
R0,1 RESISTANCE AT POSITION 2Fh () 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0 1 2 3 4 5 PROGRAMMED VALUE EEPROM RECALL >5.5M RESISTORS R0,1
DS3906 toc13
5000
2000 RESISTANCE ()
1500 RESISTOR R2 AT POSITION 1Fh 1000
500 RESISTOR R0,1 AT POSITION 2Fh 0 2.70 3.20 3.70 4.20 4.70 5.20 SUPPLY VOLTAGE (V)
POWER-SUPPLY VOLTAGE (V)
R2 RESISTANCE AT POSITION 1Fh vs. POWER-UP VOLTAGE
DS3906 toc14
R0,1 RESISTANCE AT POSITION 2Fh vs. POWER-UP VOLTAGE
R0,1 RESISTANCE AT POSITION 2Fh () 450 400 350 300 250 200 150 100 50 0 0 5 4 3 2 1 0 PROGRAMMED VALUE EEPROM RECALL RESISTOR R0,1 >5.5M
DS3906 toc15
4000 R2 RESISTANCE AT POSITION 1Fh () 3500 3000 2500 2000 1500 1000 500 0 0 1 2 3 4 5 POWER-UP VOLTAGE (V) PROGRAMMED VALUE EEPROM RECALL >5.5M RESISTOR R2
500
POWER-DOWN VOLTAGE (V)
_____________________________________________________________________
DS3906 toc11
400
15
RESISTOR R2 TEMPERATURE COEFFICIENT (ppm/C)
RESISTOR R2 TEMPERATURE COEFFICIENT (ppm/C)
RESISTOR R0,1 TEMPERATURE COEFFICIENT (+25C TO +85C) vs. RESISTOR SETTING
RESISTOR R2 TEMPERATURE COEFFICIENT (-40C TO +25C) vs. RESISTOR SETTING
RESISTOR R2 TEMPERATURE COEFFICIENT (+25C TO +85C) vs. RESISTOR SETTING
180
5
Triple NV Low Step Size Variable Resistor Plus Memory DS3906
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
R2 RESISTANCE AT POSITION 1Fh vs. POWER-UP VOLTAGE
DS3906 toc16
INL vs. RESISTOR SETTING FOR (R0 REXT)
DS3906 toc17
R2 RESISTANCE AT POSITION 1Fh ()
3500 3000
RESISTOR R2
>5.5M
1.5 1.0 INL (LSB)
(R0 REXT) REXT = 87
0.8 0.6 0.4
(R0 REXT) REXT = 87
2000 1500 1000 500 0 5 4 3 2 1 0 POWER-DOWN VOLTAGE (V) PROGRAMMED VALUE
0 -0.5 -1.0 -1.5 -2.0 0 10 20 30 40 50 RESISTOR SETTING (dec) 60
DNL (LSB)
2500
EEPROM RECALL
0.5
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 10 20 30 40 50 60 RESISTOR SETTING (dec)
INL vs. RESISTOR SETTING FOR (R1 REXT)
DS3906 toc19
DNL vs. RESISTOR SETTING FOR (R1 REXT)
0.8 0.6 0.4 DNL (LSB) (R1 REXT) REXT = 87
DS3906 toc20
2.0 1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 10 20 30 40 50 60 RESISTOR SETTING (dec) (R1 REXT) REXT = 87
1.0
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 10 20 30 40 50 60 RESISTOR SETTING (dec)
INL vs. RESISTOR SETTING FOR (R2 REXT)
DS3906 toc21
DNL vs. RESISTOR SETTING FOR (R2 REXT)
0.8 0.6 0.4 (R2 REXT) REXT = 258
DS3906 toc22
2.0 1.5 1.0 (R2 REXT) REXT = 258
1.0
0 -0.5 -1.0 -1.5 -2.0 0 10 20 30 40 50 RESISTOR SETTING (dec) 60
DNL (LSB)
INL (LSB)
0.5
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 10 30 40 50 20 RESISTOR SETTING (dec) 60
6
_____________________________________________________________________
DS3906 toc18
4000
2.0
DNL vs. RESISTOR SETTING FOR (R0 REXT)
1.0
Triple NV Low Step Size Variable Resistor Plus Memory DS3906
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME A1 SDA SCL VCC GND H2 H1 H0 A0 A2 I2C Serial Data Open-Drain Input/Output I2C Serial Clock Input Power Supply Voltage Ground High Terminal of Resistor 2 High Terminal of Resistor 1 High Terminal of Resistor 0 I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. FUNCTION I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device.
Block Diagram
VCC
Detailed Description
The DS3906 contains three variable resistors plus a user EEPROM. The block diagram illustrates these in addition to the registers that control the resistors. The following sections provide detailed information about the DS3906.
EEPROM RHIZ CONTROL H0
VCC
Memory Organization
F8h RESISTOR 0 6 LSB
DS3906
GND
MSB
RES 0 2.54k
RHIZ CONTROL
H1
The DS3906 contains 16 bytes of User EEPROM plus 3 NV resistor registers. Refer to Table 1. Communication with the memory/registers is achieved through the I2Ccompatible serial interface and is described in subsequent sections.
SCL SDA A0 A1 A2 F9h I2C INTERFACE MSB RESISTOR 1 6 LSB RES 1 2.54k
Resistor Registers/Settings
Each of the three resistors in the DS3906 has its own control register used to set the resistor position. Refer to the block diagram and Table 2. Each resistor has 64 positions plus a high impedance state. The nominal resistance values for each position is listed in Table 3. Resistors 0 and 1 have the same full-scale resistance, which is different than resistor 2. As shown in Table 3, the resistors have a pseudo-log response (resistance vs. position) when used without an external parallel resistor. Valid resistor settings are 00h to 3Fh. Writing a value greater than 3Fh to any of the resistor registers
RHIZ CONTROL
H2
USER EEPROM 16 BYTES (00h-0Fh)
FAh MSB
RESISTOR 2 6 LSB
RES 2 1.45k
_____________________________________________________________________
7
Triple NV Low Step Size Variable Resistor Plus Memory
makes the corresponding resistor go High-Z. Plots for both resistor sizes are shown on the front page of this data sheet. It can be seen that, when an external resistor is connected in parallel with the DS3906's resistors, the effective resistance is linear and capable of achieving sub-ohm and ohm steps. The resistor settings are stored in EEPROM memory. It is important to point out that the DS3906 EEPROM is organized in 2-byte pages. This is transparent when reading from the device or when performing single byte writes. However, this limits the maximum number of bytes that can be written in one I2C transaction to two. Furthermore, the multiple byte writes must begin on even memory addresses (00h, 02h, ...., F8h, etc). Additional information is provided later in the I 2 C Communication section . Example communication transactions are provided in Figure 3.
DS3906
Table 1. DS3906 Memory Map
ADDRESS 00h to 0Fh F8h F9h FAh FBh-FFh TYPE EEPROM EEPROM EEPROM EEPROM NAME User memory Resistor 0 Resistor 1 Resistor 2 Reserved Resistor 0-2 settings. See Table 2 and the Resistor Registers/Settings section. FUNCTION 16 bytes of general-purpose user EEPROM. FACTORY DEFAULT 00h 3Fh 3Fh 3Fh
Table 2. DS3906 Resistor Registers
ADDRESS F8h F9h FAh VARIABLE RESISTOR Resistor 0 Resistor 1 Resistor 2 POSITION 3FH RESISTANCE (k) 2.54 2.54 1.45 64 (00h to 3Fh) + High-Z NUMBER OF POSITIONS*
* Writing a value greater than 3Fh to any of the resistor registers makes the corresponding resistor go High-Z. Position 3Fh is the maximum position.
8
_____________________________________________________________________
Triple NV Low Step Size Variable Resistor Plus Memory DS3906
Table 3. DS3906 Resistor Settings (without external resistor)
POSITION Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F NOMINAL RESISTOR VALUES WITHOUT EXT RESISTOR (25C) Resistors 0, 1 175.0 178.8 182.7 186.8 190.9 195.2 199.6 204.2 208.9 213.7 218.8 223.9 229.3 234.9 240.6 246.6 252.8 259.2 265.9 272.8 280.0 287.5 295.3 303.5 312.0 320.8 330.1 339.8 350.0 360.7 371.9 383.7 Resistor 2 469.7 476.4 483.2 490.1 497.2 504.4 511.7 519.2 526.8 534.6 542.5 550.6 558.8 567.3 575.9 584.6 593.6 602.8 612.1 621.7 631.5 641.5 651.7 662.2 672.9 683.8 695.0 706.5 718.3 730.3 742.7 755.4 POSITION Dec 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Hex 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F NOMINAL RESISTOR VALUES WITHOUT EXT RESISTOR (25C) Resistors 0, 1 396.1 409.1 422.9 437.5 452.9 469.3 486.7 505.2 525.0 546.1 568.8 593.1 619.2 647.5 678.1 711.4 747.7 787.5 831.3 879.6 933.3 993.4 1060.9 1137.5 1225.0 1326.0 1443.8 1583.0 1750.0 1954.2 2209.4 2537.5 Resistor 2 768.4 781.7 795.4 809.4 823.9 838.7 853.9 869.6 885.7 902.3 919.4 936.9 955.1 973.7 993.0 1012.8 1033.3 1054.5 1076.4 1099.0 1122.4 1146.6 1171.7 1197.7 1224.7 1252.7 1281.7 1311.9 1343.3 1376.0 1410.1 1445.6
_____________________________________________________________________
9
Triple NV Low Step Size Variable Resistor Plus Memory DS3906
External Resistor Selection/Considerations
Using an external resistor in parallel with any of the DS3906's resistors makes the effective resistance linear with small increments from position to position. Typical values for the external resistors are 87 for Resistor 0 and 1 and 258 for Resistor 2. The effective resistance will be the most linear when these values are used. Of course these values may be tweaked to achieve the desired step size and range. The effects of changing REXT is shown on the front page. Likewise, a series resistor may be used to further customize the desired response. If the DS3906's transfer function does not meet the applications needs, contact the factory at the email address provided on the front page to inquire about custom resistance values. Figure 1. Address pins tied to GND result in a `0' in the corresponding bit position in the slave address. Conversely, address pins tied to VCC result in a `1' in the corresponding bit positions. I2C communication is described in detail in the following section.
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start and stop conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic high states. When the bus is idle it often initiates a low power mode for slave devices. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. See the timing diagram for applicable timing.
I2C Slave Address and Address Pins
The DS3906's I2C slave address is determined by the state of the A0, A1, and A2 address pins as shown in
MSB 1 0 1 0 A2 A1 A0
LSB R/W
SLAVE ADDRESS* *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
READ/WRITE BIT
Figure 1. DS3906 Slave Address Byte
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
Figure 2. I2C Timing Diagram 10 ____________________________________________________________________
Triple NV Low Step Size Variable Resistor Plus Memory
Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition, See the timing diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (see Figure 2). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 2) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 2) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7-bits and the R/W bit in the least significant bit. The DS3906's slave address is determined by the state of the A0, A1, and A2 address pins as shown in Figure 1. Address pins tied to GND result in a `0' in the corresponding bit position in the slave address. Conversely, address pins tied to VCC result in a `1' in the corresponding bit positions. When the R/W bit is 0 (such as in A0h), the master is indicating it writes data to the slave. If R/W = 1, (A1h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS3906 assumes the master is communicating with another I2C device and ignore the communication until the next start condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
DS3906
I2C Communication
Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data and generate a stop condition. Remember the master must read the slave's acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: The DS3906 is capable of writing up to 2 bytes (1-page or row) in a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 2-byte page. Pages begin on even addresses (00h, 02h, 04h, etc). Attempts to write more than 2 bytes of memory without at once without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. To write multiple bytes to a slave in one transaction, the master generates a start condition, writes the slave address byte (R/W =0), writes the memory address (must be even), writes two data bytes, and generates a stop condition. Remember the master must read the slave's acknowledgement during all byte write operations.
11
____________________________________________________________________
Triple NV Low Step Size Variable Resistor Plus Memory
Acknowledge Polling: Any time an EEPROM page is written, the DS3906 requires the EEPROM write time (tW) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3906, which allows communication to continue as soon as the DS3906 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. EEPROM Write Cycles: When EEPROM writes occur, the DS3906 internally writes the whole EEPROM page (2bytes) even if only a single byte write was performed. Writes that do not modify all 2 bytes on the page are valid and do not corrupt any of other bytes on the same page. Because the whole page is written, even bytes on the page that were not modified during the transaction are still subject to a write cycle. The DS3906's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It is capable of handling many additional writes at room temperature. Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a start condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a start condition, writes the slave address byte (R/W =0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. See Figure 3 for a read example using the repeated start condition to specify the starting memory location.
DS3906
TYPICAL I2C WRITE TRANSACTION MSB START 1 0 1 0 A2 A1 A0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER/MEMORY ADDRESS
DATA
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2. EXAMPLE I2C TRANSACTIONS (WHEN A0, A1, AND A2 ARE CONNECTED TO GND) A0h A) SINGLE BYTE WRITE -WRITE RESISTOR 1 TO 00h B) SINGLE BYTE READ -READ RESISTOR 0 F9h SLAVE 0 0 0 0 0 0 0 0 ACK SLAVE ACK A1h REPEATED START FFh SLAVE ACK 111 1 1 1 1 1 SLAVE ACK STOP 1 0 1 0 0 0 0 1 SLAVE ACK STOP
START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1 ACK A0h F8h
DATA RES 0 MASTER NACK STOP
START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE ACK ACK A0h 00h SLAVE ACK 00000 000
C) SINGLE BYTE WRITE -WRITE FIRST BYTE OF USER EEPROM TO FFh D) TWO BYTE WRITE -WRITE TWO BYTES OF USER EEPROM TO 00h
START 1 0 1 0 0 0 0 0
A0h
00h
00h 00000000 SLAVE ACK
00h 00000000 SLAVE ACK STOP
SLAVE SLAVE START 1 0 1 0 0 0 0 0 00000 000 ACK ACK A0h 00h SLAVE SLAVE 000 00000 ACK ACK
E) TWO BYTE READ -READ TWO BYTES OF USER EEPROM STARTING FROM 00h
START 1 0 1 0 0 0 0 0
REPEATED START
LOCATION 00h A1h 1 0 1 0 0 0 0 1 SLAVE DATA ACK
LOCATION 01h MASTER ACK DATA MASTER NACK STOP
Figure 3. I2C Communication Examples 12 ____________________________________________________________________
Triple NV Low Step Size Variable Resistor Plus Memory
Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it must NACK to indicate the end of the transfer and generates a stop condition. and 0.1F. Use a high-quality, ceramic, surface-mount capacitor, and mount it as close as possible to the VCC and GND pins of the I.C. to minimize lead inductance.
DS3906
High Resistor Terminal Voltage
It is permissible to have a voltage on the resistor-high terminals that is higher than the voltage connected to VCC. For instance, connecting VCC to 3.0V while one or more of the resistor high terminals are connected to 5.0V allows a 3V system to control a 5V system. The 5.5V maximum still applies to the limit on the resistor high terminals regardless of the voltage present on VCC.
Application Information
Power Supply Decoupling
To achieve best results, it is highly recommended that a decoupling capacitor is used on the I.C. power supply pins. Typical values of decoupling capacitors are 0.01F
Typical Operating Circuit
GREEN LED PANEL RED LED PANEL LED DRIVERS 300 300 300 300 300 300 LED DRIVERS 300 300 BLUE LED PANEL LED DRIVERS 300 300 300 300
H0 VCC 0.1F VCC H1 4.7k FROM SYSTEM CONTROLLER 4.7k SCL SDA A0 A1 A2 GND R0 REXT0 = 105
DS3906 R1
REXT1 = 105
H2 R2 REXT2 = 310
DESIGN NOTES: 1. IN THIS APPLICATION A NUMBER OF LED DRIVERS ARE SET USING THE DS3906'S VARIABLE RESISTORS. 2. THE PARALLEL COMBINATION OF THE DS3906 VARIABLE RESISTOR R0 AND 105 (REXT0) IS EQUIVALENT TO A VARIABLE RESISTOR WITH LINEAR STEP INCREMENTS OF 0.6 RANGING FROM 66 TO 101. THE SAME APPLIES FOR RESISTOR 1 (R1). THE PARALLEL COMBINATION OF R2 AND 310 (REXT2) IS EQUIVALENT TO A VARIABLE RESISTOR WITH LINEAR STEP INCREMENTS OF 1 RANGING FROM 187 TO 255. 3. VALUES LARGER THAN THE SHOWN EXTERNAL RESISTORS (REXT0, REXT1, AND REXT2) RESULT IN LARGER STEP INCREMENTS AND RESISTOR VALUES LOWER THAN THE SHOWN VALUES RESULT IN SMALLER STEP INCREMENTS. REFER TO THE RESISTOR TABLES AND COMPUTE EQUIVALENT RESISTANCE TO FIND OUT THE RANGES.
____________________________________________________________________
13
Triple NV Low Step Size Variable Resistor Plus Memory DS3906
Chip Topology
TRANSISTOR COUNT: 16,200 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.

▲Up To Search▲

Price & Availability of DS3906

	To Download DS3906 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .